威盛集团威睿电通校招职位

VIATelecom

简历接收邮箱：recruit-bj@via-telecom.com,，注明应聘职位
VTCBJ-01 Audio Engineer
职位编码：VTCBJ-01
招聘部门： Chipset
工作地点：北京
注：本职位有笔试安排
职位描述和要求：
[Responsibilities]
1, Algorithm research and development for speech enhancement, such as echo cancellation, noise suppression, multi-mic noise cancellation;
2. Research and develop new audio/voice algorithm based on customer requirements;
3. Audio/Voice codec implementation and optimization;
4. Join audio software design and create design document;
[Requirements]
1. MS or above degree required, in Electrical Engineering, Signal Processing, Computer Science or related major;
2. Good understanding with speech enhancement, such as acoustic echo cancellation, noise suppression and microphone array processing;
3. Be familiar with audio/voice codec standard is preferred, such as MP3, AAC, EVRC, AMR or other codec;
4. Be familiar with audio effect algorithm is preferred, such as equalization, 3D surround.
5. Good English communication skills, team working.
2. VTCBJ-03 Physical Layer Software Engineer
职位编码：VTCBJ-03
招聘部门： Chipset
工作地点：北京
注：本职位有笔试安排
职位描述和要求：
[Job Descriptions]
Responsible for SW development for Physical Layer of wireless communication system.
[Requirements]
1.2+ years experiences of DSP software development.
2. Experienced in designing, implementing, testing, debugging and integrating real time embedded software/firmware for wireless communications physical layer functions.
3. Strong programming skills both in C and assembly.
4. Solid background knowledge about wireless communication and digital signal processing.
5. Master degree in EE, Communication or equivalent.
3. VTCBJ-05 System Engineer
职位编码：VTCBJ-05
招聘部门： Chipset
工作地点：北京
注：本职位有笔试安排
职位描述和要求：
[Responsibilities]
1、Develop wireless communication system-level/link-level algorithms and simulators to support standard or product development.
2、Support product development and prototyping.
3、Create IP (intellectual property).
[Requirements]
1、Good understanding of basic linear systems (filtering, Fourier transforms, discrete time signal processing), plus experience in most of the following areas: modulation and demodulation; channel coding and decoding; Rake receiver, equalizer, interference cancellation, information theory; wireless network topology and traffic queuing; adaptive retransmission schemes; signal propagation, and channel characterization; antennas array and diversity; CDMA; OFDM; MAC layer scheduling and the co-design with physical layer.  
2、Must be able to analyze system performance and compare design alternatives in the link level (physical layer and MAC) and/or system level (voice and packet data system capacity including upper layer).
3、Familiarity with IS-95, IS-2000, GSM, or WCDMA, Wimax and 4G is a plus.
4、Strong computer simulation skills using C/C++ is a must. Matlab experience is preferred.
5、The team member should also be capable of estimating his/her own schedule, and managing work to that schedule
6、A Master degree majoring in communications systems with a high average score is minimum
7、A Ph.D. degree majoring in communications systems with a high average score is preferable
4. VTCBJ-06 ASIC Engineer
职位编码：VTCBJ-06
招聘部门： ASIC
工作地点：北京
注：本职位有笔试安排
职位描述和要求：
[Responsibilities]
1、Composing function/logic specification from datasheet or industry standard.
2、Listing test item from function/logic specification; Making test plan according test item.
3、Composing testcase/testcode based on test plan.
4、Logic implementation based on function/logic specification.
[Requirements]
1、Knowledge of ASIC design including: Logic implementation using Verilog HDL; Basic knowledge of Logic synthesis and Timing analysis; Basic knowledge of ASIC/FPGA design flow.
2、Experience in writing C.
3、Good spoken and written English skills.
4、Careful observer with an orderly mind; Strong self-study capability.
5、The following items are plus:
a) Experience in FPGA implementation
b) Knowledge of multimedia, such as MPEG video/audio, image process, graphic process, etc
c) Be familiar with System Verilog and UVM
d) Be familiar with ISP
6、M.S/degree in Computer Science, Electrical engineering, Automation, Communication.

5. VTCBJ-07 RFIC Engineer
职位编码：VTCBJ-07
招聘部门： ASIC
工作地点：北京
注：本职位有笔试安排
职位描述和要求
Responsibilities
1.        RFIC system design and spec budgeting
2.        RFIC system and circuit co-simulation building
3.        RFIC calibration and compensation methodology creation
4.        RFIC testing environment setup and debugging
Requirement
1.        M.S degree required, in EE or signal and system
2.        Basic knowledge of digital signal process
3.        Basic knowledge of RF IC design
4.        Good English communication skills, team working.